Verilog-AMS
id:
verilog-ams-319-18470266
title:
Verilog-AMS
text:
Verilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.
brand slug:
wiki
category slug:
encyclopedia
description:
Hardware description language building on Verilog for mixed-signal integrated circuit
original url:
https://en.wikipedia.org/wiki/Verilog-AMS
date created:
date modified:
2023-05-31T10:03:27Z
main entity:
{"identifier":"Q1971841","url":"https://www.wikidata.org/entity/Q1971841"}
image:
fields total:
13
integrity:
14