TILEPro64
id:
tilepro64-204-15518753
title:
TILEPro64
text:
TILEPro64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a cache-coherent mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the co
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/TILEPro64
date created:
2010-10-28T17:09:57Z
date modified:
2024-09-10T14:56:36Z
main entity:
{"identifier":"Q7670389","url":"https://www.wikidata.org/entity/Q7670389"}
image:
{"content_url":"https://upload.wikimedia.org/wikipedia/commons/d/dc/TILEPro64_TileBlock.JPG","width":268,"height":240}
fields total:
13
integrity:
15