Level-sensitive scan design
id:
level-sensitive-scan-design-289-18108217
title:
Level-sensitive scan design
text:
Within the field of electronics Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing test process. It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held
brand slug:
wiki
category slug:
encyclopedia
description:
Part of an integrated circuit manufacturing test process
original url:
https://en.wikipedia.org/wiki/Level-sensitive_scan_design
date created:
date modified:
2022-04-04T14:50:17Z
main entity:
{"identifier":"Q6534985","url":"https://www.wikidata.org/entity/Q6534985"}
image:
fields total:
13
integrity:
14