Latency oriented processor architecture
id:
latency-oriented-processor-architecture-200-18643444
title:
Latency oriented processor architecture
text:
Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to
brand slug:
wiki
category slug:
encyclopedia
description:
Microarchitecture of a microprocessor designed to serve a serial computing thread with low latency
original url:
https://en.wikipedia.org/wiki/Latency_oriented_processor_architecture
date created:
date modified:
2023-01-29T15:51:04Z
main entity:
{"identifier":"Q28455699","url":"https://www.wikidata.org/entity/Q28455699"}
image:
fields total:
13
integrity:
14