High-level verification
id:
high-level-verification-319-15569993
title:
High-level verification
text:
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis, HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL i
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/High-level_verification
date created:
date modified:
2020-01-13T20:48:40Z
main entity:
{"identifier":"Q5754573","url":"https://www.wikidata.org/entity/Q5754573"}
image:
fields total:
13
integrity:
13