Delay-insensitive minterm synthesis
id:
delay-insensitive-minterm-synthesis-265-3562229
title:
Delay-insensitive minterm synthesis
text:
Within digital electronics, the DIMS system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the quasi-delay-insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to represent each bit of data. This is known as a dual-rail data encoding. Parts of the system communicate using the early four-phase asynchronous protocol. The construction of DIMS logic gates comprises generat
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/Delay-insensitive_minterm_synthesis
date created:
date modified:
2022-02-25T20:20:44Z
main entity:
{"identifier":"Q5253469","url":"https://www.wikidata.org/entity/Q5253469"}
image:
{"content_url":"https://upload.wikimedia.org/wikipedia/en/c/c6/Dims_gate.png","width":640,"height":460}
fields total:
13
integrity:
14