Delay insensitive circuit
id:
delay-insensitive-circuit-266-14024816
title:
Delay insensitive circuit
text:
A delay-insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in delay-insensitive circuit is determined by the data flow. Data flows from one circuit element to another using "handshakes", or sequences of voltage transitions to indicate readiness to receive data, or readiness to offer data. Typically, inputs of a circuit
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/Delay_insensitive_circuit
date created:
date modified:
2018-08-22T17:35:38Z
main entity:
{"identifier":"Q5253475","url":"https://www.wikidata.org/entity/Q5253475"}
image:
fields total:
13
integrity:
13