Cray T3E
id:
cray-t3e-257-11492278
title:
Cray T3E
text:
The Cray T3E was Cray Research's second-generation massively parallel supercomputer architecture, launched in late November 1995. The first T3E was installed at the Pittsburgh Supercomputing Center in 1996. Like the previous Cray T3D, it was a fully distributed memory machine using a 3D torus topology interconnection network. The T3E initially used the DEC Alpha 21164 (EV5) microprocessor and was designed to scale from 8 to 2,176 Processing Elements (PEs). Each PE had between 64 MB and 2 GB of D
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/Cray_T3E
date created:
date modified:
2023-12-28T02:36:16Z
main entity:
{"identifier":"Q1139187","url":"https://www.wikidata.org/entity/Q1139187"}
image:
{"content_url":"https://upload.wikimedia.org/wikipedia/commons/0/0d/T3E-900t.jpg","width":800,"height":586}
fields total:
13
integrity:
14