Cray MTA
id:
cray-mta-257-5522298
title:
Cray MTA
text:
The Cray MTA, formerly known as the Tera MTA, is a supercomputer architecture based on thousands of independent threads, fine-grain communication and synchronization between threads, and latency tolerance for irregular computations. Each MTA processor (CPU) has a high-performance ALU with many independent register sets, each running an independent thread. For example, the Cray MTA-2 uses 128 register sets and thus 128 threads per CPU/ALU. All MTAs to date use a barrel processor arrangement, with
brand slug:
wiki
category slug:
encyclopedia
description:
original url:
https://en.wikipedia.org/wiki/Cray_MTA
date created:
date modified:
2021-02-17T19:59:58Z
main entity:
{"identifier":"Q5183021","url":"https://www.wikidata.org/entity/Q5183021"}
image:
fields total:
13
integrity:
13